Substrates which comprise a silicon carbide layer are being used increasingly in standard components. For example, power semiconductors which block up to voltages of more than 1.2 kV are produced as trench metal oxide semiconductor field-effect transistors (trench MOSFETs) by using such substrates. Such power semiconductors are used, for example, in electro-mobile applications, i.e. motor vehicles with batteries, for example batteries based on lithium ion cells, or in photovoltaic systems. Microelectromechanical systems may also be produced with such substrates. For microelectromechanical systems, the substrate may furthermore comprise a silicon dioxide layer, a silicon nitride layer or a silicon layer, on which the silicon carbide layer is deposited.
In order to produce a trench MOSFET, for example, a substrate (monocrystalline n-doped 4H-SiC substrate) is used, the silicon carbide layer of which has a hexagonal crystal structure and is n-doped. An n-doped silicon carbide buffer layer is arranged between the silicon carbide layer and a weakly n-doped silicon carbide drift zone (n-drift zone).
Such production of a trench MOSFET 100 according to the prior art is shown in FIG. 1. Arranged on then-doped 4H-SiC substrate 10, there is a moderately p-doped silicon carbide layer (p−-layer) 20, which may be epitaxially grown or implanted. Arranged on a part of the p−-layer 20, there is a heavily n-doped silicon carbide layer (n+-source) 30 which may be epitaxially grown or implanted and is used as a source terminal. In this case, a rear side of the 4H-SiC substrate 10 is used as a drain terminal. Next to the n+-source 30, a p+-terminal (p+-plug) 40 is implanted as far as into the p−-layer 20, so that an upper side of the p+-plug 40 follows on from the upper side of the n+-source 30 and the p+-plug 40 can be used for defining a channel potential. The p−-layer 20 and the n+-source 30 are respectively structured by a recess, which is arranged over a trench with which the n-drift zone 10 is structured. The recesses have an equal constant width in cross section. Apart from a bottom region, the trench also has the same width. Only in the bottom region does the width of the trench taper because of the structuring, so that the trench has a cup-shaped profile in cross section. The trench is also concave in cross section.
After the structuring, the trench may be coated with a gate oxide. As an alternative or in addition, a heavily doped implantation may be carried out in the bottom of the trench. A polysilicon gate 50 is then deposited into the trench. A vertical channel region 25 is thus formed in the p−-layer 20. This allows a higher packing density of parallel-connected transistors than in the case of transistors with a lateral channel region.
The transition, due to the structuring, from the side wall of the trench to the bottom of the trench may lead in the application to very high field strengths in this region, which are greater than the breakdown threshold at which the oxide layer is electrically broken through in the off state and the component is damaged.